Expand description
Types for unwinding on the aarch64 CPU architecture.
Structs
- The Aarch64 CPU architecture.
- The unwinder cache type for
UnwinderAarch64
. - Aarch64 CPUs support special instructions which interpret pointers as pair of the pointer address and an encrypted hash: The address is stored in the lower bits and the hash in the high bits. These are called “authenticated” pointers. Special instructions exist to verify pointers before dereferencing them.
- The registers used for unwinding on Aarch64. We only need lr (x30), sp (x31), and fp (x29).
- The unwinder for the Aarch64 CPU architecture. Use the
Unwinder
trait for unwinding.