Module uart

Source

Structsยง

Uart

Enumsยง

UartPort
UartReg ๐Ÿ”’

Constantsยง

IE_RX_READY ๐Ÿ”’
IE_TX_READY ๐Ÿ”’
LINE_BAUD_LATCH ๐Ÿ”’
Enables the divisor latch access bit
LINE_RX_READY ๐Ÿ”’
Got data
LINE_TX_EMPTY ๐Ÿ”’
Transmitter is empty
MODEM_CTL_DTR ๐Ÿ”’
Controls the Data Terminal Ready Pin
MODEM_CTL_LOOPBACK ๐Ÿ”’
Controls the loopback mode
MODEM_CTL_OUT1 ๐Ÿ”’
Controls the Out1 pin
MODEM_CTL_OUT2 ๐Ÿ”’
Controls the Out2 pin (used for interrupts)
MODEM_CTL_RTS ๐Ÿ”’
Controls the Request To Send Pin

Functionsยง

init_port ๐Ÿ”’
Will return true if the test pass, otherwise, the serial port is disabled
read_reg ๐Ÿ”’
write_reg ๐Ÿ”’