#[repr(C, align(8))]struct E1000Mmio {Show 70 fields
control: RW<u32>,
_pad0: Pad<4>,
status: RO<u32>,
_pad1: Pad<4>,
eecd: RW<u32>,
eerd: RW<u32>,
ctrl_ext: RW<u32>,
flash: RW<u32>,
mdi_control: RW<u32>,
_pad2: Pad<4>,
flow_control_addr_low: RW<u32>,
flow_control_addr_high: RW<u32>,
flow_control_type: RW<u32>,
_pad3: Pad<4>,
vlan_ethertype: RW<u32>,
_pad4: Pad<0x82>,
interrupt_cause_read: RW<u32>,
interrupt_throttling: RW<u32>,
interrupt_cause_set: RW<u32>,
_pad5: Pad<4>,
interrupt_mask_set: RW<u32>,
_pad6: Pad<4>,
interrupt_mask_clear: WO<u32>,
_pad7: Pad<0x24>,
receive_control: RW<u32>,
_pad8: Pad<0x6C>,
flow_control_transmit_timer: RW<u32>,
_pad9: Pad<4>,
transmit_config_word: RW<u32>,
_pad10: Pad<4>,
receive_config_word: RO<u32>,
_pad11: Pad<0x27C>,
transmit_control: RW<u32>,
_pad12: Pad<0x9FC>,
led_control: RW<u32>,
_pad13: Pad<0x160C>,
receive_data_fifo_head: RW<u32>,
_pad14: Pad<0x4>,
receive_data_fifo_tail: RW<u32>,
_pad15: Pad<0x4>,
receive_data_fifo_head_saved: RW<u32>,
_pad16: Pad<0x4>,
receive_data_fifo_tail_saved: RW<u32>,
_pad17: Pad<0x4>,
receive_data_fifo_packet_count: RW<u32>,
_pad18: Pad<0x3CC>,
receive_descriptor_base_low: RW<u32>,
receive_descriptor_base_high: RW<u32>,
receive_descriptor_length: RW<u32>,
_pad19: Pad<0x4>,
receive_descriptor_head: RW<u32>,
_pad20: Pad<0x4>,
receive_descriptor_tail: RW<u32>,
_pad21: Pad<0x4>,
receive_delay_timer: RW<u32>,
_pad22: Pad<0x8>,
receive_interrupt_abs_delay_timer: RW<u32>,
_pad23: Pad<0xFD0>,
transmit_descriptor_base_low: RW<u32>,
transmit_descriptor_base_high: RW<u32>,
transmit_descriptor_length: RW<u32>,
_pad24: Pad<0x4>,
transmit_descriptor_head: RW<u32>,
_pad25: Pad<0x4>,
transmit_descriptor_tail: RW<u32>,
_pad26: Pad<0x4>,
transmit_descriptor_interrupt_delay: RW<u32>,
_pad27: Pad<0x19DC>,
multicast_table_array: [RW<u32>; 128],
receive_addresses: [(RW<u32>, RW<u32>); 16],
}
Fields§
§control: RW<u32>
§_pad0: Pad<4>
§status: RO<u32>
§_pad1: Pad<4>
§eecd: RW<u32>
§eerd: RW<u32>
§ctrl_ext: RW<u32>
§flash: RW<u32>
§mdi_control: RW<u32>
§_pad2: Pad<4>
§flow_control_addr_low: RW<u32>
§flow_control_addr_high: RW<u32>
§flow_control_type: RW<u32>
§_pad3: Pad<4>
§vlan_ethertype: RW<u32>
§_pad4: Pad<0x82>
§interrupt_cause_read: RW<u32>
§interrupt_throttling: RW<u32>
§interrupt_cause_set: RW<u32>
§_pad5: Pad<4>
§interrupt_mask_set: RW<u32>
§_pad6: Pad<4>
§interrupt_mask_clear: WO<u32>
§_pad7: Pad<0x24>
§receive_control: RW<u32>
§_pad8: Pad<0x6C>
§flow_control_transmit_timer: RW<u32>
§_pad9: Pad<4>
§transmit_config_word: RW<u32>
§_pad10: Pad<4>
§receive_config_word: RO<u32>
§_pad11: Pad<0x27C>
§transmit_control: RW<u32>
§_pad12: Pad<0x9FC>
§led_control: RW<u32>
§_pad13: Pad<0x160C>
§receive_data_fifo_head: RW<u32>
§_pad14: Pad<0x4>
§receive_data_fifo_tail: RW<u32>
§_pad15: Pad<0x4>
§receive_data_fifo_head_saved: RW<u32>
§_pad16: Pad<0x4>
§receive_data_fifo_tail_saved: RW<u32>
§_pad17: Pad<0x4>
§receive_data_fifo_packet_count: RW<u32>
§_pad18: Pad<0x3CC>
§receive_descriptor_base_low: RW<u32>
§receive_descriptor_base_high: RW<u32>
§receive_descriptor_length: RW<u32>
§_pad19: Pad<0x4>
§receive_descriptor_head: RW<u32>
§_pad20: Pad<0x4>
§receive_descriptor_tail: RW<u32>
§_pad21: Pad<0x4>
§receive_delay_timer: RW<u32>
§_pad22: Pad<0x8>
§receive_interrupt_abs_delay_timer: RW<u32>
§_pad23: Pad<0xFD0>
§transmit_descriptor_base_low: RW<u32>
§transmit_descriptor_base_high: RW<u32>
§transmit_descriptor_length: RW<u32>
§_pad24: Pad<0x4>
§transmit_descriptor_head: RW<u32>
§_pad25: Pad<0x4>
§transmit_descriptor_tail: RW<u32>
§_pad26: Pad<0x4>
§transmit_descriptor_interrupt_delay: RW<u32>
§_pad27: Pad<0x19DC>
§multicast_table_array: [RW<u32>; 128]
§receive_addresses: [(RW<u32>, RW<u32>); 16]
Auto Trait Implementations§
impl !RefUnwindSafe for E1000Mmio
impl Send for E1000Mmio
impl !Sync for E1000Mmio
impl Unpin for E1000Mmio
impl UnwindSafe for E1000Mmio
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